描述

140CPU31110 交流同服的技術(shù)本身就是借鑒并應(yīng)用了變頻的技術(shù)

140CPU31110模塊
交流同服的技術(shù)本身就是借鑒并應(yīng)用了變頻的技術(shù)，在直流電機的伺服控制的基礎(chǔ)上通過變頻的PWM方式模仿直流電機的控制方式來實現(xiàn)的，也就是說交流同服電機必然有變頻的這一環(huán)節(jié):變頻就是將工頻的50、60HZ的交流電先整流成直流電，然后通過可控制門極的各類晶體管(IGBT，IGCT等)通過載波頻率和PWM調(diào)節(jié)逆變?yōu)轭l率可調(diào)的波形類以于正余弦的脈動電，由于頻率可調(diào)，所以交流電機的速度就可調(diào)了 (n=60f/p，n轉(zhuǎn)速，傾率，p極對數(shù))

140CPU31110模塊

CPU的分類還可以按照指令集的方式將其分為精簡指令集計算機(RISC)和復(fù)雜指令集計算機(CISC)。RISC指令長度和執(zhí)行時間恒定，CISC指令長度和執(zhí)行時間不一定。 RISC 指令的并行的執(zhí)行程度更好，并且編譯器的效率也較高。CISC指令則對不同的任務(wù)有著更好的優(yōu)化，代價是電路復(fù)雜且較難提高并行度，典型的CISC指令集有x86微架構(gòu)，典型的RISC指令集有ARM微架構(gòu)。但在現(xiàn)代處理器架構(gòu)中RISC和CISC指令均會在譯碼環(huán)節(jié)進行轉(zhuǎn)換，拆分成CPU內(nèi)部的米RISC指今

140CPU31110 交流同服的技術(shù)本身就是借鑒并應(yīng)用了變頻的技術(shù)

40CPU31110 Module
The technology of AC co-service itself is to learn from and apply the technology of frequency conversion, which is realized by imitating the control mode of DC motor through the PWM mode of frequency conversion on the basis of the servo control of DC motor, that is to say, AC co-service motor must have the link of frequency conversion: frequency conversion is the power frequency of 50, 60HZ AC power first rectified into direct current. Then through the control gate of all kinds of transistors (IGBT, IGCT, etc.) through the carrier frequency and PWM to adjust the inverter frequency adjustable waveform class to the sine and cosine pulse electricity, because the frequency is adjustable, so the speed of the AC motor is adjustable (n=60f/p, n speed, tilt rate, p pole number)

140CPU31110 Module

The classification of cpus can also be divided into reduced instruction set computers (RISC) and complex instruction set computers (CISC) in terms of instruction sets. RISC instruction length and execution time are constant, CISC instruction length and execution time are not necessarily. The parallel execution of RISC instructions is better, and the compiler is more efficient. CISC instructions are better optimized for different tasks, but the cost is that the circuit is complex and difficult to improve the parallelism. Typical CISC instruction set has x86 microarchitecture, and typical RISC instruction set has ARM microarchitecture. However, in modern processor architectures, RISC and CISC instructions are converted in the decoding process, and are split into the internal RISC of the CPU

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